1. Field of the Invention
The present invention relates to a package to package data transmission system for transmitting digital signals between a plurality of printed circuit boards (referred to as "packages", hereinafter) on each of which a plurality of LSIs such as CPUs, memories and address generation circuits and other electronic parts are mounted, and, particularly, to a data transmission system for transmitting digital data between a CPU package and a peripheral control package performing data transmission and reception.
2. Description of the Prior Art
In an information processing apparatus having hardware and software whose functions are being improved, a distributed processing system using microprocessor (CPU) has been employed in order to realize required improvement of functions thereof efficiently and economically. In general, such distributed processing system is constituted with a central processing unit for controlling a whole system and a peripheral processing unit for controlling respective peripheral functions. CPUs used in the central processing unit and the peripheral processing unit are being improved functionally with an increase of bit number, such as from 4-bit model to 8-bit model, to 16-bit model and to 32-bit model.
Each of such central processing unit and peripheral processing unit is constituted, generally, with a CPU package for controlling a whole function of the unit and a plurality of peripheral control packages for performing peripheral control functions under control of the CPU package. Of course, each peripheral control package may include a CPU according to a desired function or functions.
A data transfer between the CPU package and the peripheral control packages is an important design parameter since it affects service functions available by the system, performance of the system and the number of packages.
An example of conventional data transmission of this type is to change transmission rate of a channel interface of a data transmission device, such as RS-232C interface, according to specific applications. In such conventional method, since an amount of control information is small, a CPU and an I/O port are mounted on the CPU package, memories and data transmission devices are mounted on the peripheral control packages, such that the transmission rate of the data transmission device is set by polling it from the CPU through the I/O port and the memories.
As another conventional method, a setting of TSI (Time Slot Interchange) in a time division multiplexer which is one of the data transmission device is changed according to applications. Since the control of TSI is to assign time slots each of several tens Mbps for respective transmission routes, it is necessary to set a large amount of information within a short time. In this method, the CPU package mounts a CPU for operating setting locations of the time slots and the peripheral control packages mount shared memories, CPUs for performing controls according to operation information and handshaking registers through which the respective CPUs conflict in getting right of control to transmit data through the shared memories.
In the first example mentioned, a CPU having control right has to determine, prior to a data transmission, whether or not a destination apparatus is available for data reception. On the other hand, in the second example, there is always conflict in getting control right between CPUs of a transmitting apparatus and a receiving apparatus. In either of these conventional systems, a CPU having control right is used for transmitting processing until a data transmission completes and therefore a load on the CPU side is increased. Particularly, when an amount of data is large or there are a plurality of peripheral control packages in the destination apparatus, increase of load becomes considerable. Further, since the data transmission is performed by the CPU on data by data basis, it takes a long time to complete transmission. In addition, since, in the conventional systems, each data is transmitted only once, it is very difficult to detect, in the CPU, a data error which occurs externally in the destination apparatus due to occurrences such as lightning. Such data error becomes a very large problem in a data transmission apparatus which is to be run continuously for 24 hours.